Multiple supply voltage select circuit for reduced supply voltage levels
US7521987B1 · kind B1 · utility
5Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2007 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Dec 3, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17788
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Multiple supply voltage select circuit for use with reduced supply voltage levels and method for using same are described. A first and second set of P-channel transistors are used for voltage pull-up at a common node using two supply voltages, respectively. A P-channel transistor from each of the sets is gated by output of a respective level shifter. Both of the level shifters are biased with a higher of the two supply voltages. First and second inputs are respectively provided to the level shifters and to gates of other P-channel transistors of each of the sets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.