Biasing current to speed up current mirror settling time
US7522002B2 · kind B2 · utility
0Cited by
20References
23Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 4, 2007 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Mar 27, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G3/3225
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A current mirror circuit includes a first current-mirror transistor coupled to a second current-mirror transistor. A load is coupled to the second current-mirror transistor. A first current source is coupled to the first current-mirror transistor to cause a bias current to flow through the first current-mirror transistor and a second current source is coupled to the second current-mirror transistor and in parallel with the load to shunt the bias current away from the load.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.