Non-volatile memory with source-side column select
US7522453B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2007 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Dec 27, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory array segment includes an odd-select transistor having a drain coupled to an odd-source line and an even-select transistor having a drain coupled to an even-source line. Two segment-select transistors have drains coupled to the sources of different ones of the odd and even source lines, sources coupled to ground, and gates coupled to a segment-select line. A plurality of odd non-volatile memory transistors each has a drain coupled to a common drain line, a source coupled to the odd-source line, a floating gate, and a control gate. A plurality of even non-volatile memory transistors, each has a drain coupled to the common drain line, a source coupled to the even-source line, a floating gate, and a control gate. The control gate of each even non-volatile memory transistor is coupled to the control gate of a different one of the odd non-volatile memory transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.