Method and system for reducing soft-writing in a multi-level flash memory
US7522455B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2005 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Oct 27, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for reducing soft-writing in a multilevel flash memory during read or verify includes a memory cell. A first and second reference cells are coupled to the memory cell and are configured to receive a first and a second voltage. A current comparison circuit is coupled to the first and second reference cells and to the memory cell and is configured to compare current flow through the memory cell with current flow through the first and second reference cells, and to determine whether the memory cell holds a first range of values while the first reference cell receives the first voltage, and if the memory cell does not hold the first range of values, to determine whether the memory cell holds a second range of values while the second reference cell receives the second voltage, thereby reducing soft-writing during the read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.