Sense amplifier with stages to reduce capacitance mismatch in current mirror load
US7522463B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2007 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Feb 1, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.