Device and method for maximizing performance on a memory interface with a variable number of channels
US7523230B1 · kind B1 · utility
1Cited by
35References
8Claims
0Family size
Inventors
Key dates
| Filing date | May 24, 2005 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | May 24, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.