System and method for testing for memory address aliasing errors
US7523291B2 · kind B2 · utility
1Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2005 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | May 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aliasing errors, occasioned by, for example, a programming error resulting in including extra or missing bits in a storage address, wrong addressing mode, or wrong address context, are detected by providing a storage address configuration including gaps in valid addresses. Such a programming error is detected and an exception is thrown (that is, an addressing error is detected and indicated) responsive to an address reference to such a gap in valid addresses. Gaps are configured at complementary address ranges to facilitate detection of such aliasing errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.