Channel masking during integrated circuit testing
US7523370B1 · kind B1 · utility
36Cited by
6References
42Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 15, 2004 |
| Grant date | Apr 21, 2009 |
| Priority date | — |
| Expiry date | Oct 10, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318547
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
During testing of an integrated circuit (IC), a channel masking capability is used for masking out unknown or unpredictable (X) values from being compressed into a signature register. The approach provides flexibility to allow for masking of unknown values, while avoiding many of the problems caused by over-masking of known values. The circuitry added to the design to allow for masking is reasonably small, and provides an effective way of masking unknown values during the testing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.