Methods of manufacturing printed circuit boards with stacked micro vias
US7523545B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2007 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | May 5, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Methods of manufacturing printed circuit boards having circuit layers laminated with stacked (or staggered) micro via(s). Aspects of embodiments of the present invention are directed to a method of manufacturing a printed circuit board with Z-axis interconnect(s) or micro via(s) that can eliminate a need for plating micro vias and/or eliminate a need for planarizing plated bumps of a surface, that can be fabricated with one or two lamination cycles, and/or that can have carrier-to-carrier (or substrate-to-substrate) attachments with conductive vias, each filled with a conductive material (e.g., with a conductive paste) in the Z-axis. In one embodiment, a printed circuit board having a plurality of circuit layers with at least one z-axis interconnect can be fabricated using a single lamination cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.