Localized strain relaxation for strained Si directly on insulator
US7524740B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2008 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Apr 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a localized region of relaxed Si in a layer of strained Si arranged within a strained silicon directly on insulator (SSDOI) semiconductor substrate is provided by the invention. The strained Si layer is formed on a buried oxide (BOX) layer disposed on a Si substrate base. The method includes depositing a nitride hard mask pattern above a region of the strained Si layer in which enhanced electron mobility is desired, leaving an unmasked region within the strained Si layer, and carrying out various other processing steps to modify and relax the unmasked portion of the strained region. The method includes growing an EPI SiGe region upon the unmasked region using pre-amorphization implantation, and forming a buried amorphous SiGe region in a portion of the EPI SiGe region, and an amorphous Si region, below the amorphous SiGe region. Then, using SPE regrowth, modifying the amorphous SiGe and amorphous Si regions to realize an SPE SiGe region and relaxed SPE Si layer. The SiGe region and the SPE SiGe region are etched, leaving the relaxed SPE Si region above the buried oxide layer. The nitride pattern is stripped.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.