JFET device with virtual source and drain link regions and method of fabrication
US7525136B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2007 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | May 3, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/328
Abstract
A junction field effect transistor comprises a semiconductor substrate. A source region of a first conductivity type is formed in the substrate. A drain region of the first conductivity type is formed in the substrate. A channel region of the first conductivity type is formed in the substrate. A gate region of a second conductivity type is formed in the substrate between the source and drain regions. A first virtual link region is formed in the substrate between the gate region and either the source region or the drain region. A dielectric material overlays the first virtual link region. A first electrode region overlays the dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.