High voltage double diffused drain MOS transistor with medium operation voltage
US7525150B2 · kind B2 · utility
7Cited by
14References
11Claims
0Family size
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Key dates
| Filing date | Apr 7, 2004 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Apr 29, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
Abstract
A method of fabricating a high voltage MOS transistor with a medium operation voltage on a semiconductor wafer. The transistor has a double diffused drain (DDD) and a medium operation voltage such as 6 to 10 volts, which is advantageous for applications having both low and higher operation transistor devices. The second diffusion region of the DDD is self-aligned to the spacer on the sidewalls of the gate and gate dielectric, so that the transistor size may be decreased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.