Barrier process/structure for transistor trench contact applications
US7525197B2 · kind B2 · utility
3Cited by
7References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2006 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Mar 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76831
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A barrier architecture is provided that includes different materials that are selected to be employed in connection with copper contact applications. Some of the barrier material is formed over trench contact sidewalls, and other different barrier material is formed over trench contact bottoms. By selecting the appropriate barrier materials, electromigration can be improved while, at the same time, interconnect and contact resistances can be kept low and array leakage can be mitigated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.