Duty cycle correction amplification circuit
US7525359B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 2006 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Sep 30, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/023
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A duty cycle correction amplification circuit is disclosed and comprises a first amplifier comprising dual first MOS differential input transistors gated respectively by first and second reference signals, and adapted to generate first and second preliminary signals, a second amplifier comprising dual second MOS differential input transistors respectively gated by first and second preliminary signals and adapted to generate first and second internal signals, and a duty cycle corrector adapted to correct a duty cycle associated with the first and second internal signals, wherein one of the first and second internal signals comprises an amplified output signal having a corrected duty cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.