Semiconductor storage device
US7525829B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2006 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Oct 31, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4013
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor storage device that is capable of utilizing dummy cells effectively and enhancing the memory cell density. Every second row of bit lines (second bit lines) in terminal memory mats 101A, 101C is not connected to first sense amplifiers SA1. Second sense amplifiers SA2 are arranged on the outside of the terminal memory mats, and second bit lines are connected according to a folded bit line system to the second sense amplifiers SA2. Two memory cells provided at the points where a word line WL intersects with a pair of bit lines BL, /BL connected to the second sense amplifiers SA2 constitute a twin cell unit TWC for storing a single bit of data in complementary fashion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.