Testing address lines of a memory controller
US7526689B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 2006 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Jun 26, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
All the address lines in a data processing system can be tested by using one or more small memory device that do not occupy the full addressing capability of the address lines. In one embodiment, some of the address inputs of the memory device is connected to different address lines at different times. Instructions are pre-loaded into some locations of the memory device such that the address lines has to be asserted to fetch the instructions for execution. By executing the instructions and appropriately connecting the address lines to the address input, all the address lines can be tested. In another embodiment, some of the locations are pre-loaded with a set of predetermined values. A program then writes another set of predetermined values to associated locations. By reading the values in the locations and compared with the sets of predetermined values, it is possible to determine if the address lines are functioning properly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.