Method of test pattern generation in IC design simulation system
US7526703B2 · kind B2 · utility
0Cited by
6References
12Claims
0Family size
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Key dates
| Filing date | Jul 11, 2006 |
| Grant date | Apr 28, 2009 |
| Priority date | — |
| Expiry date | Jul 25, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318307
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The invention provides a method of test pattern generation for an integrated circuit (IC) design simulation system, comprising merging at least 2 test vectors into a merged vector, wherein each test defines a set of test behaviors, and compiling and linking the merged vector using the IC design simulation system to generate a merged test pattern able to perform each set of test behaviors independently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.