Method of forming fin field effect transistor using damascene process
US7528022B2 · kind B2 · utility
5Cited by
6References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2005 |
| Grant date | May 5, 2009 |
| Priority date | — |
| Expiry date | May 5, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26586
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a fin transistor using a damascene process is provided. A filling mold insulation pattern is recessed to expose an upper portion of a fin, and a mold layer is formed. The mold layer is patterned to form a groove crossing the fin and exposing a part of the upper portion of the fin. A gate electrode is formed to fill the groove with a gate insulation layer interposed between the fin and the gate electrode, and the mold layer is removed. Impurities are implanted through both sidewalls and a top surface of the upper portion of the fin disposed at opposite sides of a gate electrode to form a source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.