Temperature dependent clamping of a transistor
US7528645B2 · kind B2 · utility
6Cited by
6References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2007 |
| Grant date | May 5, 2009 |
| Priority date | — |
| Expiry date | Sep 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2017/0806
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus, comprising a transistor having a source/drain node and a gate, and a circuit coupled between the source/drain node and the gate and configured to limit a voltage between the source/drain node and the gate to a clamping voltage such that the clamping voltage is reduced in response to a rising temperature of the transistor. Also, a method, comprising measuring a first temperature, measuring a second temperature, and reducing a clamped voltage between a source/drain node of a transistor and a gate of the transistor responsive to a difference between the first and second temperatures increasing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.