Nonvolatile memory device and semiconductor device
US7529126B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2006 |
| Grant date | May 5, 2009 |
| Priority date | — |
| Expiry date | Jun 23, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1iA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1iA to flow a current in the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.