Single-poly non-volatile memory
US7529132B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2007 |
| Grant date | May 5, 2009 |
| Priority date | — |
| Expiry date | Nov 2, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single-poly non-volatile memory includes a storing node, a control node and a floating gate. While a programming operation is executed, a bit line is provided with a low voltage and a control line is provided with a high voltage so that a coupling voltage occurs in the floating gate. The voltage difference between the floating gate and the storing node is able to send electrons into the floating gate, but the voltage difference between the floating gate and the control node is not enough to expel electrons from the floating gate. While an erasing operation is executed, a bit line is provided with a high voltage and a control line is provided with a low voltage so that a coupling voltage occurs on the floating gate. The voltage difference between the floating gate and the storing node is able to expel electrons from the floating gate, but the voltage difference between the floating gate and the control node is not enough to send electrons into the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.