Method for compacting the erased threshold voltage distribution of flash memory devices during writing operations
US7529136B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Aug 24, 2007 |
| Grant date | May 5, 2009 |
| Priority date | — |
| Expiry date | Oct 21, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/344
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating a flash memory device. The memory device includes a matrix of memory cells each one having a programmable threshold voltage defining a value stored in the memory cell. The method includes the steps of erasing a block of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell of the block for writing a target value; restoring the threshold voltage of a subset of the memory cells of the block to the compacting range, the subset including the at least one first memory cell and/or at least one second memory cell of the block being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.