Method for reading electrically programmable and erasable memory cells, with bit line precharge-ahead
US7529145B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2005 |
| Grant date | May 5, 2009 |
| Priority date | — |
| Expiry date | Aug 25, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method for reading memory cells by means of sense amplifiers, the memory cells being linked to bit lines, the reading of each memory cell comprising a phase of precharging the bit line to which the memory cell is linked and a phase of actually reading the memory cell. According to the present invention, each sense amplifier is used to precharge at least two bit lines, then to read one memory cell in one of the precharged bit lines. The present invention applies particularly to serial memories, for the precharge-ahead of bit lines having the same partial address, while a read address is being received.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.