Methods and devices employing metal layers in gates to introduce channel strain
US7531398B2 · kind B2 · utility
3Cited by
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29Claims
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Key dates
| Filing date | Oct 19, 2006 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Dec 31, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A semiconductor device is fabricated having a metal stress inducing layer that facilitates channel mobility. A gate dielectric layer is formed over a semiconductor substrate. The metal stress inducing layer is formed over the gate dielectric layer. The metal stress inducing layer has a selected conductivity type and is formed and composed to yield a select stress amount and type. A gate layer, such as a polysilicon layer, is formed over the metal stress inducing layer. The gate layer and the metal stress inducing layer are patterned to define gate structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.