Michael F. Pas
21Patents
7h-index
15Co-inventors
66Inventor score
Filing activity: Oct 4, 1996 → Aug 7, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7795097B2 | Semiconductor device manufactured by removing sidewalls during replacement gate integration scheme | Electricity | 57 | Active |
| US8525386B2 | Dynamically adjustable orthotic device | Electricity | 12 | Active |
| US5803980A | De-ionized water/ozone rinse post-hydrofluoric processing for the prevention of silicic acid residue | Electricity | 12 | Expired |
| US8749115B2 | Dynamically adjustable orthotic device | Electricity | 11 | Active |
| US6054684A | Ultra fast temperature ramp up and down in a furnace using interleaving shutters | Chemistry; Metallurgy | 10 | Expired |
| US7642153B2 | Methods for forming gate electrodes for integrated circuits | Electricity | 9 | Active |
| US7416949B1 | Fabrication of transistors with a fully silicided gate electrode and channel strain | Electricity | 8 | Active |
| US8114728B2 | Integration scheme for an NMOS metal gate | Electricity | 6 | Active |
| US7629212B2 | Doped WGe to form dual metal gates | Electricity | 4 | Active |
| US7807522B2 | Lanthanide series metal implant to control work function of metal gate electrodes | Electricity | 3 | Active |
| US7858459B2 | Work function adjustment with the implant of lanthanides | Electricity | 3 | Active |
| US7531398B2 | Methods and devices employing metal layers in gates to introduce channel strain | Electricity | 3 | Active |
| US8304333B2 | Method of forming a high-k gate dielectric layer | Electricity | 2 | Active |
| US10068786B1 | Data structures for semiconductor die packaging | Electricity | 2 | Active |
| US8304342B2 | Sacrificial CMP etch stop layer | Emerging Cross-Sectional Technologies | 2 | Active |
| US8748246B2 | Integration scheme for dual work function metal gates | Electricity | 1 | Active |
| US7799669B2 | Method of forming a high-k gate dielectric layer | Electricity | 1 | Active |
| US10658211B2 | Data structures for semiconductor die packaging | Electricity | 0 | Active |
| US8802519B2 | Work function adjustment with the implant of lanthanides | Electricity | 0 | Active |
| US8409943B2 | Work function adjustment with the implant of lanthanides | Electricity | 0 | Active |
| US8629021B2 | Integration scheme for an NMOS metal gate | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.