Methods of manufacturing semiconductor memory devices including a vertical channel transistor
US7531412B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2005 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Feb 3, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.