Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US7531828B2 · kind B2 · utility
112Cited by
52References
27Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 13, 2006 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Oct 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8162
Abstract
A semiconductor device may include at least one pair of spaced apart stress regions, and a strained superlattice layer between the at least one pair of spaced apart stress regions and including a plurality of stacked groups of layers. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.