Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7531829B2 · kind B2 · utility
111Cited by
45References
25Claims
0Family size
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Key dates
| Filing date | Sep 22, 2006 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Nov 14, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8181
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device may include a substrate and spaced apart source and drain regions defining a channel region therebetween in the substrate. The substrate may have a plurality of spaced apart superlattices in the channel and/or drain regions. Each superlattice may include a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.