Delay locked loop circuit and method
US7532050B2 · kind B2 · utility
10Cited by
68References
44Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2007 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Oct 4, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.