Integrated circuit, cell arrangement, method of operating an integrated circuit, memory module
US7532506B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 17, 2007 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Nov 2, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1675
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having a cell arrangement is provided. The cell arrangement includes at least one magnetoresistive memory cell, a first line providing a first line current, and a second line providing a second line current. The cell arrangement further includes a controller controlling the application of the first line current and the second line current, such that while the first line current is active, a transition of a magnetic field provided by a change of the second line current is provided such that the transition time of the magnetic field is shorter than the time required for the magnetization of the magnetoresistive memory cell to relax into a changed equilibrium state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.