Receiver operable to receive data at a lower data rate
US7532645B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2005 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Sep 9, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0338
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver that includes: an oversampling module that converts a serial stream of data into a plurality of streams of oversampled data based on the receive clock; a transition location module that determines transition locations of the streams of oversampled data and the receive clock; a pointer adjust module that determines a pointer variable based on the transition locations and the receive clock; a data selection module that determines an equivalent data value for the streams of oversampled data based on the pointer variable; a staging register module that produces an offset data word and an extra data word from the equivalent data value for the oversampled data streams; and a output register module that produces a parallel data output from at least one of the offset data word and the extra data word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.