Variable size cache memory support within an integrated circuit
US7533241B2 · kind B2 · utility
2Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2006 |
| Grant date | May 12, 2009 |
| Priority date | — |
| Expiry date | Nov 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit 2 is provided with a cache memory 6 and a cache controller 10 coupled to the cache memory 6 via a cache memory interface 8. The cache controller supports different cache memory sizes. The cache memory 6 includes masking logic 14 responsive to cache memory size signals to form masked address values for use in accessing the cache memory 6. The cache controller 10 can be part of a processor core 4 which may be hardened in its design and yet able to cope with variable cache memory sizes since the masking logic 14 is provided within the cache memory 6 outside of the hardened periphery of the processor core 4.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.