Florent Begon
22Patents
4h-index
27Co-inventors
59Inventor score
Filing activity: Mar 29, 2006 → Dec 28, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7925868B2 | Suppressing register renaming for conditional instructions predicted as not executed | Physics | 18 | Active |
| US7590826B2 | Speculative data value usage | Physics | 10 | Active |
| US7624253B2 | Determining register availability for register renaming | Physics | 8 | Active |
| US7600077B2 | Cache circuitry, data processing apparatus and method for handling write access requests | Physics | 5 | Active |
| US7533241B2 | Variable size cache memory support within an integrated circuit | Physics | 2 | Active |
| US8769251B2 | Data processing apparatus and method for converting data values between endian formats | Physics | 2 | Active |
| US8578139B2 | Checkpointing long latency instruction as fake branch in branch prediction mechanism | Physics | 2 | Active |
| US10528355B2 | Handling move instructions via register renaming or writing to a different physical register using control flags | Physics | 2 | Active |
| US7552285B2 | Line fill techniques | Physics | 1 | Active |
| US8352794B2 | Control of clock gating | Emerging Cross-Sectional Technologies | 1 | Active |
| US7568072B2 | Cache eviction | Emerging Cross-Sectional Technologies | 1 | Active |
| US7587556B2 | Store buffer capable of maintaining associated cache information | Emerging Cross-Sectional Technologies | 1 | Active |
| US7941608B2 | Cache eviction | Emerging Cross-Sectional Technologies | 0 | Active |
| US9513925B2 | Marking long latency instruction as branch in pending instruction table and handle as mis-predicted branch upon interrupting event to return to checkpointed state | Physics | 0 | Active |
| US12141069B2 | Prefetch store filtering | Physics | 0 | Active |
| US8458532B2 | Error handling mechanism for a tag memory within coherency control circuitry | Emerging Cross-Sectional Technologies | 0 | Active |
| US7844800B2 | Method for renaming a large number of registers in a data processing system using a background channel | Physics | 0 | Active |
| US11086781B2 | Methods and apparatus for monitoring prefetcher accuracy information using a prefetch flag independently accessible from prefetch tag information | Physics | 0 | Active |
| US9189432B2 | Apparatus and method for predicting target storage unit | Physics | 0 | Active |
| US9542194B2 | Speculative register file read suppression | Physics | 0 | Active |
| US11900121B2 | Methods and apparatus for predicting instructions for execution | Physics | 0 | Active |
| US11138119B2 | Increasing effective cache associativity | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.