Recessed poly extension T-gate
US7534706B2 · kind B2 · utility
5Cited by
9References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 6, 2006 |
| Grant date | May 19, 2009 |
| Priority date | — |
| Expiry date | Aug 6, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for making a silicided gate in a semiconductor device. In accordance with the method, a gate (213) is provided which comprises a first portion (214) and a second portion (213). The first portion of the gate has a width w1 and the second portion of the gate has a width w2 as taken along a plane perpendicular to the length of the gate, wherein w2>w1. A layer is silicide (231) is then formed on the second portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.