Method and apparatus for packaging circuit devices
US7535093B1 · kind B1 · utility
6Cited by
12References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2002 |
| Grant date | May 19, 2009 |
| Priority date | — |
| Expiry date | Jul 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16153
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A hermetically sealed package includes a lid (14) hermetically bonded to a wafer or substrate (12), with a chamber therebetween defined by a recess (16) in the lid. A circuit device (26) such as MEMS device is provided within the chamber on the substrate. A plurality of vias (41-46) are provided through the substrate, and each have a structure which facilitates a hermetic seal of a suitable level between opposite sides of the substrate. The vias provide electrical communication from externally of the assembly to the device disposed in the chamber.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.