Stack die packages
US7535110B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2007 |
| Grant date | May 19, 2009 |
| Priority date | — |
| Expiry date | Jun 21, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuit packages having corresponding methods comprise: a substrate comprising first electric contacts; a first wirebond integrated circuit die mechanically coupled to the substrate and comprising second electric contacts electrically coupled to the first electric contacts of the substrate by first electrically conductive wires; a flip-chip integrated circuit die comprising third electric contacts electrically coupled to the second electric contacts of the first wirebond integrated circuit die by electrically conductive bumps; and a second wirebond integrated circuit die mechanically coupled to the flip-chip integrated circuit die and comprising fourth electric contacts electrically coupled to the second electric contacts of the first wirebond integrated circuit die, or the first electric contacts of the substrate, or both, by second electrically conductive wires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.