Interface test circuit

US7535242B2 · kind B2 · utility

Assignee

• Rambus Inc. · US

Inventors

• Bret G. Stott · Menlo Park, US
• Philip Yeung · Mountain View, US
• John Brooks · San Jose, US
• Benedict Lau · San Jose, US
• Chanh Tran · San Jose, US
• Eugene C. Ho · San Jose, US

Key dates

• Filing date: May 3, 2006
• Grant date: May 19, 2009
• Expiry date: Dec 22, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C29/022
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.