Register data retention systems and methods during reprogramming of programmable logic devices
US7535253B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2007 |
| Grant date | May 19, 2009 |
| Priority date | — |
| Expiry date | Jan 31, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in accordance with an embodiment, a method includes programming routing resources between programmable logic and registers of a programmable logic device to provide a data path for data prior to a reprogramming; transferring data from the programmable logic, prior to the reprogramming, to the registers via the data path to store the data within the programmable logic device during the reprogramming; reprogramming the programmable logic device, wherein the reprogramming provides a reprogrammed data path between the programmable logic and the registers of the programmable logic device; and transferring the data within the programmable logic device from the registers via the reprogrammed data path for use by the programmable logic after the reprogramming of the programmable logic device has been completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.