Sampling error reduction in PWM-MASH converters
US7535393B1 · kind B1 · utility
2Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2007 |
| Grant date | May 19, 2009 |
| Priority date | — |
| Expiry date | Nov 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques for reducing sampling error in electronic components are described herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.