Low power memory hierarchy for high performance video processor
US7536487B1 · kind B1 · utility
22Cited by
2References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 11, 2005 |
| Grant date | May 19, 2009 |
| Priority date | — |
| Expiry date | May 24, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An apparatus generally having an internal memory and an external transfer circuit is disclosed. The internal memory may be disposed on a chip and may contain at least one first buffer for storing a subset of at least one reference frame (i) suitable for motion compensation and (ii) stored in an external memory off the chip. A size of the at least one first buffer generally exceeds one row of blocks in the reference frame. The external transfer circuit may be disposed on the chip and configured to transfer the subset from the external memory to the internal memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.