Method and apparatus for discovering hardware in a data processing system
US7536539B2 · kind B2 · utility
2Cited by
5References
1Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 5, 2004 |
| Grant date | May 19, 2009 |
| Priority date | — |
| Expiry date | May 20, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus and computer instructions for discovering hardware nodes having a hierarchical organization. A subset of the hardware nodes in the data processing system is initialized prior to loading an operating system supporting parallel threads. In response to loading the operating system, thread for each hardware node discovered below a known hardware node is created to form a set of threads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.