Todd A. Venton
22Patents
6h-index
28Co-inventors
65Inventor score
Filing activity: Aug 5, 2004 → Sep 10, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8108655B2 | Selecting fixed-point instructions to issue on load-store unit | Physics | 146 | Active |
| US8135942B2 | System and method for double-issue instructions using a dependency matrix and a side issue queue | Physics | 36 | Active |
| US8103852B2 | Information handling system including a processor with a bifurcated issue queue | Physics | 35 | Active |
| US9134966B2 | Management of mixed programming languages for a simulation environment | Physics | 30 | Active |
| US8131980B2 | Structure for dynamic livelock resolution with variable delay memory access queue | Physics | 15 | Active |
| US8296739B2 | Testing soft error rate of an application program | Physics | 13 | Active |
| US8239661B2 | System and method for double-issue instructions using a dependency matrix | Physics | 6 | Active |
| US7991979B2 | Issuing load-dependent instructions in an issue queue in a processing unit of a data processing system | Physics | 6 | Active |
| US7346809B2 | Bootable post crash analysis environment | Physics | 5 | Expired |
| US7536539B2 | Method and apparatus for discovering hardware in a data processing system | Physics | 2 | Expired |
| US7805636B2 | Bootable post crash analysis environment | Physics | 2 | Active |
| US8099582B2 | Tracking deallocated load instructions using a dependence matrix | Physics | 2 | Active |
| US8037366B2 | Issuing instructions in-order in an out-of-order processor using false dependencies | Physics | 2 | Active |
| US10552323B1 | Cache flush method and apparatus | Emerging Cross-Sectional Technologies | 1 | Active |
| US7272759B2 | Method and apparatus for system monitoring with reduced function cores | Physics | 1 | Expired |
| US8078999B2 | Structure for implementing speculative clock gating of digital logic circuits | Emerging Cross-Sectional Technologies | 0 | Active |
| US7401262B2 | Method and apparatus for a low-level console | Physics | 0 | Expired |
| US9395992B2 | Instruction swap for patching problematic instructions in a microprocessor | Physics | 0 | Active |
| US9519480B2 | Branch target preloading using a multiplexer and hash circuit to reduce incorrect branch predictions | Physics | 0 | Active |
| US7823028B2 | Low-level console interface | Physics | 0 | Active |
| US8020072B2 | Method and apparatus for correcting data errors | Physics | 0 | Active |
| US7971161B2 | Apparatus and method for implementing speculative clock gating of digital logic circuits | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.