Method and apparatus for providing secure programmable logic devices
US7536559B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2005 |
| Grant date | May 19, 2009 |
| Priority date | — |
| Expiry date | Aug 3, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for providing secure programmable logic devices is described. One aspect of the invention relates to securing a programmable logic device having instruction register logic coupled to control logic via an instruction bus. A non-volatile memory is provided for storing at least one security bit for at least one instruction associated with the programmable logic device. Gating logic is provided in communication with the non-volatile memory and at least a portion of the instruction bus. The gating logic is configured to selectively gate decoded instructions transmitted from the instruction register logic towards the control logic based on state of the at least one security bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.