Incremental placement during physical synthesis
US7536661B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2006 |
| Grant date | May 19, 2009 |
| Priority date | — |
| Expiry date | May 3, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of optimizing a portion of a circuit design for a target device can include identifying a critical region from a plurality of regions after an initial placement of the circuit design. The critical region can be defined, at least in part, by at least one input block and at least one output block. Blocks of the critical region can be relocated to different sites within the critical region. The method further can include evaluating the relocation of blocks of the critical region according to a cost function and continuing to relocate blocks and evaluate the relocation of blocks in the critical region until at least one exit criterion is met.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.