Circuit configurations to reduce snapback of a transient voltage suppressor
US7538997B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 31, 2006 |
| Grant date | May 26, 2009 |
| Priority date | — |
| Expiry date | Jul 21, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D8/80
Abstract
This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage. In a preferred embodiment, the triggering Zener diode, the BJT and the rectifier are formed in a semiconductor substrate by implanting and configuring dopant regions of a first and a second conductivity types in a N-well and a P-well whereby the TVS can be formed in parallel as part of the manufacturing processes of the electronic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.