Semiconductor memory device including plurality of memory mats
US7539036B2 · kind B2 · utility
2Cited by
11References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 30, 2007 |
| Grant date | May 26, 2009 |
| Priority date | — |
| Expiry date | Jan 30, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a plurality of memory mats each including a memory cell storing data, a sense latch portion performing detection of data stored by the memory cell, and a buffer circuit externally outputting read data detected by the sense latch portion. The sense latch portion and the buffer circuit are shared between a plurality of memory mats and are arranged between a plurality of memory mats.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.