Selective bit line precharging in non volatile memory
US7539059B2 · kind B2 · utility
8Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2006 |
| Grant date | May 26, 2009 |
| Priority date | — |
| Expiry date | Feb 14, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells with strings of memory cells connected to respective bitlines. Structures and methods for selectively pre-charging bitlines are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.