Binary stream switching controlled modulus divider for fractional frequency synthesis
US7539277B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 9, 2005 |
| Grant date | May 26, 2009 |
| Priority date | — |
| Expiry date | Jul 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A modulus divider controller coupled to a modulus divider for generating a synthesized clock from a reference clock, wherein the modulus divider generates a divided clock, is provided. The modulus divider controller may further include a first binary stream switching circuit having a first output and a second output. The first binary stream switching circuit may further have a logic low input and a logic high input and a first switching input corresponding to a most significant bit of a count generated by a synchronous counter, wherein the synchronous counter counts the divided clock. The first binary stream switching circuit may further have a second switching input corresponding to a least significant bit of a division control word, wherein the division control word specifies a fractional division ratio for the synthesized clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.