Handling concurrent address translation cache misses and hits under those misses while maintaining command order
US7539840B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2006 |
| Grant date | May 26, 2009 |
| Priority date | — |
| Expiry date | Feb 28, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method handles concurrent address translation cache misses and hits under those misses while maintaining command order based upon virtual channel. Commands are stored in a command processing unit that maintains ordering of the commands. A command buffer index is assigned to each address being sent from the command processing unit to an address translation unit. When an address translation cache miss occurs, a memory fetch request is sent. The CBI is passed back to the command processing unit with a signal to indicate that the fetch request has completed. The command processing unit uses the CBI to locate the command and address to be reissued to the address translation unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.