Integrated circuit testing using segmented scan chains
US7539915B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 3, 2003 |
| Grant date | May 26, 2009 |
| Priority date | — |
| Expiry date | Apr 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31855
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit, and associated method and computer program, comprises a first scan chain portion comprising a plurality of first storage elements to interconnect in series according to a signal applied to a scan shift node of the integrated circuit, an input in communication with a scan input node of the integrated circuit, and an output; a second scan chain portion comprising a plurality of second storage elements to interconnect in series according to the signal applied to the scan shift node of the integrated circuit, an input in communication with the output of the first scan chain portion, and an output; and a switch comprising a first input in communication with the output of the first scan chain portion, a second input in communication with the output of the second scan chain portion, and a switch output in communication with a scan output node of the integrated circuit, wherein the switch is to place one of the first and second inputs in communication with the switch output according to a signal applied to a scan mode node of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.